The present invention relates to electronic circuits. More particularly, the present invention relates to novel and improved integrated circuits and devices that process digital and analog signals.
In many applications, analog circuitry and digital circuitry are required. Examples are digital radios, optical communications chips, and digital signal processors (DSPs).
In these applications, integrated circuits (ICs) such as very large scale integrated (VLSI) circuits containing digital and analog signal processing circuitry are employed. These ICs are sometimes referred to as mixed signal ICs. The digital signal processing circuitry may include both low-voltage circuitry where the digital supply voltage typically is 1.0-2.0 Volts and high-voltage circuitry where, as with the analog signal processing circuitry, the supply voltage is larger than 2 V.
Field-effect transistors (FETs), specifically those of the Metal-Oxide Semiconductor (MOS) type, constitute the main active circuit elements currently used in ICs. This is also the case for CMOS (Complementary Metal-Oxide Semiconductor) circuit implementations.
The operational characteristics of FETs in the analog and high-voltage digital portions typically differ from the characteristics of FETs in the low-voltage digital portions.
FETs used in the low-voltage digital circuitry of an IC are typically manufactured at the minimum gate length that can be reliably formed and still yield acceptable electrical performance characteristics. Device miniaturization has brought the minimum gate length down to 0.1-0.2 xcexcm. As the minimum gate length is reduced, physical parameters such as gate dielectric thickness, source/drain junction depth, net channel doping, threshold voltage, and supply voltage are adjusted together according to appropriate scaling rules. This enables the transistors to be fabricated at small dimensions without the deleterious effects, such as non-saturating output characteristics, threshold-voltage dependence on channel length, and drain-induced current leakage, that are associated with short-channel FETs.
Up to now, a manufacturing process used to fabricate low-voltage FETs for an IC must also provide differently designed FETs that can perform analog functions at higher voltages. The IC designs where the FETs of the digital signal processing circuitry and the FETs of the analog signal processing circuitry are operated at different supply voltages are complicated and expensive.
Quite often one has to employ the same FETs in the analog signal processing circuitry and the digital signal processing circuitry of a digital CMOS integrated circuit. This leads to situations where FETs in the analog signal processing circuitry are operated at a bias voltage significantly below the maximum allowed supply voltage (Vmax). The signal-to-noise (S/N) ratio may thus not be acceptable anymore.
In modern MOS and CMOS processes, the maximum allowed supply voltage (herein called VDDmax) is determined by reliability considerations for the application of transistors (FETs) in standard digital gates. The requirement is that any voltage difference across the nodes of the transistors does not go beyond a certain limit Vmax. The relevant voltages for an n-channel FET 10 are depicted in FIG. 1. The voltage between the gate 11 and the drain 12 is called VGD, the voltage between the drain 12 and the source 14 is called VDS, and the voltage between the gate 11 and the source 14 is called VGS. All the voltages have to be below Vmax for the FET 10 to operate reliably. For digital gates this requires Vmax to be the maximum allowed supply voltage of the whole IC chip. The voltages towards the bulk 13 are not limited to the same extent.
If the same FETs are being used in the analog signal processing circuitry, this requires the signal swing to stay within the limits posed by the maximum allowed supply voltage Vmax. With supply voltages going down further with the advance of smaller geometry this has a severe impact on the achievable dynamic signal range, i.e., the S/N ratio is getting worse.
On the other hand, in analog signal processing circuitry the voltages across transistor nodes are not necessarily equal to the supply voltage of the whole IC chip. An example is given in FIG. 2. This Figure shows a well known differential amplifier 20 being frequently used throughout analog signal processing in operation amplifiers (OpAmps), comparators, etc.
The signal on nodes VIN121 and VIN222, respectively, must not exceed a value of Vsupplydiffxe2x88x92Vsxe2x88x92Vt1 for proper operation. Vt1=Vt2 represent the gate to source voltages (VGS) for the input transistors 23 and 24 in saturation (i.e., close to the threshold value). Vs is the source to drain voltage (VSD) across the transistor 25 serving as current mirror. It is a disadvantage of the present circuit 20 that the allowed signal swing of the analog signals on the nodes VIN121 and VIN222 are many hundred millivolts below the supply voltage Vsupply. On the other hand, all voltages across the transistors 23 and 24 never reach the value of Vsupply.
It is on object of the present invention to provide mixed signal integrated circuits with an improved analog signal processing performance.
It is on object of the present invention to provide a digital CMOS integrated circuit comprising analog signal processing circuitry where the signal swing in the analog signal processing circuitry is allowed to cover the whole supply voltage range between zero Volts and the maximum allowed supply voltage (Vmax).
According to the present invention, a voltage is generated by a local charge pump and locally added to the chip supply so as to allow analog signal swings to range between 0 Volts and the FET""s maximum allowed supply voltage value (Vmax).
Local charge pumps are presented herein that allow to generate the required elevated voltages. A local charge pump, according to the present invention, converts pulses into charge stored on a capacitor. This charge is then used to generate the elevated voltage. By locally increasing the supply for some transistor nodes of the analog signal processing circuitry, the dynamic signal range of the respective portion of the analog signal processing circuitry is increased.
In other words, a scheme is proposed which allows the supply of analog signal processing circuitry with local charge pumps beyond the maximum allowed supply voltage (Vmax) of a submicron or deep submicron process keeping the voltage across any individual FET below the Vmax.